Our partner, a direct collaborator in the RISC-V architecture, is actively involved in a fierce battle against the "monopoly" ARM, leading companies like Google to consider shifting their future processors towards this architecture. This move addresses the growing need to incorporate AI into chips for mobiles, tablets, smartwatches, and ultimately any IoT device in the future. They are currently seeking to add talented individuals like you to their team.Today, they boast highly specialized professionals in this field and have forged alliances with key industry partners, in addition to running their own training academy to nurture critical talent for their business. They are currently looking to onboard Senior Talent and Leads, and they invite you to be part of this exciting journey as a Senior Verification EngineerYour responsibility lies within the Verification Team, where you'll play a vital role in validating the correctness and functionality of intricate digital designs at the Register Transfer Level (RTL) as per specifications. Utilizing advanced verification techniques and tools, you'll ensure the validation of designs with precision and accuracy.Job description (responsibilities):Verification PlanningTestbench DevelopmentVerification Environment SetupTest Execution and DebuggingCoverage AnalysisVerification MethodologiesDesired knowledge:Proficiency in SystemVerilog and UVM-Knowledge of uArchitectureKnowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools-Experience of RTL LintingExperience with simulation and simulation toolsKnowledge of revision control methodology and tools (git, svn)Experience in block level and sub-system or top level verificationExperience with formal and dynamic verificationStrong problem-solving skills and attention to detailExcellent communication and teamwork abilitiesPreferred/Valued knowledge:-Knowledge of RISC-V and RISC-V Vector ExtensionExperience with GLSKnowledge of the JIRA toolExperience with ASIC and FPGA designKnowledge of C++Type: PermanentCategory: ITDate Posted: 2024-03-26